PI: Dr. Jia Di
This project is to analyze the HDL format of an IC design, determine all its functionalities, and identify any malicious insertions. Due to the massive outsourcing of IC design and fabrication, malicious logic could be inserted at various stages in the IC manufacturing flow such that in addition to the functionalities listed in the specification, the fabricated IC would be able to perform unwanted functions, which jeopardize the security of the system employing this IC. This is especially true for DoD electronic systems. It has been funded by Defense Advanced Research Projects Agency (DARPA)
Development of an Ultra-Low Power IC Design and Packaging Technique to Provide a Variety of Critical Anti-Tamper Safeguards
PI: Dr. Jia Di, co-PI: Dr. Scott C. Smith
This project plans to develop a digital IC design methodology and tool flow for mitigating Side-Channel Attacks (SCAs), which decipher the crypto key stored on a crypto IC in a non-invasive manner via the statistical analysis of its power-, timing-, electromagnetic-, and fault-data. The proposed technology is the Multi-Threshold Dual-spacer Dual-rail Delay-insensitive asynchronous Logic (MTD3L), which perfectly balances the switching activities among different data patterns, thereby decouples the relationship between the data and the IC's performance measurements, rendering SCAs very difficult to succeed. The MTCMOS structure brings low-power as an additional feature. It has been funded by Air Force.
Understanding Security Flows in the Manycore Era
PI: Dr. David Andrews
This research project seeks to lay the groundwork for automating the flow of security properties between technologies during the system integration in such a fashion that will allow the formal security properties to flow through the complete design and integration process. The long term goal of this research project is to lay the groundwork to automate the flow through of security properties during the design and integration process. To this end, our short term goals are: develop a framework for automated reasoning of formal security properties within CAD tool chains, develop a run-time system for evaluating and guaranteeing security properties for many-core systems on chip platforms, develop a refinement flow that allows additional functionality to be linked in during the transformation of high level security properties into a realizable and running system. This has been funded by Naval Research Laboratory.
Fingerprinting RFID Tags with Transfer-of-Ownership Capabilities
PI: Dr. Dale R. Thompson, co-PI: Dr. Jia Di
The goals of this research are to develop lightweight electronic fingerprinting primitives to prevent counterfeiting of low-cost passive UHF RFID tags and to develop hardware-based primitives to transfer ownership of tags based on the fingerprint. In this work, we propose to move authentication of a tag from something it "possesses" to something the device "is." We use the term electronic fingerprinting because, like human fingerprinting, we measure features of the tag that are inherently unique because of manufacturing variances. The research will lead to secure and private contactless identification and transfer of ownership of objects.
This material is based upon work supported by the National Science Foundation, CISE/CNS Trustworthy Computing area, under Grant No. CNS-1053286
Detection of Insider Threats at Application Levels
PI: Dr. Brajendra Panda
The objective of this research proposal is to develop an Insider Threat
Analysis Model to work at application levels. For this project we have
selected Database Systems as the application for which the insider threat
analysis architecture and necessary protocols will be developed. We plan to carry out six important tasks. They are:
| (1) design and development of the insider threat detection unit architecture, | |
| (2) development and analysis of the method for acquiring knowledge by verifying data item values in the database, checking various integrity constraints, and by examining transaction semantics, | |
| (3) development and analysis of techniques to understand relationships among data items, among transactions, and between transactions and data items, | |
| (4) development of protocols to identify critical assets, i.e., data items, which must be protected carefully, | |
| (5) analyzing the minimal set of data items a transaction would need at a given time to carry out its assigned tasks, and | |
| (6) development and analysis of a model that conforms each user's access to appropriate items. |
RFID Information Systems Security (INFOSEC)
PI: Dr. Dale Thompson, co-PI: Dr. Jia Di
Radio frequency identification (RFID) information systems provide information to users about objects with RFID tags. RFID systems require the application of information systems security (INFOSEC) to protect the information from tampering, unauthorized information disclosure, and denial of service to authorized users. Typically, students experience only narrowly focused layers of a RFID system such as the tag, air interface, reader, network, middleware, or applications in separate courses instead of a system-wide approach. The goal of this project is to improve the quality of education nation-wide in RFID INFOSEC by creating new learning materials and teaching strategies that address security at the tag, air interface, reader, network, middleware, and application layers. The principal investigators are Drs. Dale R. Thompson (d.r.thompson@ieee.org) and Jia Di (jdi@uark.edu). Senior investigators are Drs. Michael K. Daugherty and Craig W. Thompson. This work was supported by the National Science Foundation Division of Undergraduate Education under the Course, Curriculum and Laboratory Improvement (CCLI) program, contract DUE-0736741
Project website: http://rfidsecurity.uark.edu.
Anti-Counterfeiting RFID Tags
PI: Dr. Dale Thompson, co-PI: Dr. Jia Di
RFID tags embedded in objects will become the standard way to identify objects to provide the link between the physical and cyber worlds. However, it is easy to clone RFID tags by copying the contents of the memory to a new tag to create a counterfeit tag that can be attached to a counterfeit product. In addition, RFID tags are vulnerable to side-channel attacks in which external parameters such as power consumption and timing delays are measured to calculate the desired information. The objective of the anti-counterfeiting RFID tag research is to prevent counterfeiting of RFID tags by offering mitigating techniques that provide different levels of protection and have different requirements in cost and implementation complexity in order to provide appropriately secure and flexible solutions for different applications. The anticipated results of this high-risk and high-payoff area of research are cost-effective and reliable anti-counterfeiting techniques to prevent cloning of RFID tags. The principal investigators are Drs. Dale R. Thompson (d.r.thompson@ieee.org) and Jia Di (jdi@uark.edu). This work was supported by the National Science Foundation CISE/CNS and the Cyber Trust area support under contract CNS-0716578.
Hardware Threat Modeling for Integrated Circuits
PI: Dr. Jia Di
The impact of software viruses has been felt by the entire computerized world. Hardware, on the other hand, was considered safe and attack-free. However, as technologies advance and markets expand, hardware is becoming vulnerable like software. Malicious logic could be inserted into a circuit like a Trojan horse such that it lies dormant and is very difficult to detect until activated, but then cannot be effectively defeated. This project is to develop a methodology and software tool to model the potential threats/attacks of a given digital system, and to search for and mitigate malicious logic inserted.
Mitigating Side-Channel Attacks to Digital ICs
PI: Dr. Jia Di
As part of the anti-counterfeiting RFID tags project, this research is to mitigate power- and timing-based side-channel attacks. In contrast to invasive attacks to digital ICs, side-channel attacks do not require the target to be physically de-packaged. Instead, attackers can monitor the fluctuations of certain external parameters such as power consumption and timing delay caused by different data being processed. The recorded data will be analyzed to calculate the desired information. This project is to develop a power-/timing-attack mitigation technique by designing digital ICs using Dual-spacer Dual-rail Delay-insensitive asynchronous Logic (D3L) to balance the power consumption and obfuscate the timing delays among different data patterns, thus rendering these attacks useless. Three versions of the Advanced Encryption Standard (AES) core, namely, synchronous, traditional delay-insensitive asynchronous (NULL Convention Logic), and D3L, will be designed, attacked, and compared. The results will be analyzed for the effectiveness and efficiency of the mitigation.
Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection
PI: Dr. Jia Di and Scott Smith
The goal of this research is to develop a universal solution that synergistically combines both architecture-level and circuit-level countermeasures for mitigating all four major categories of side-channel attacks (i.e., power, timing, EM emissions, and fault injection), which works for any underlying cryptographic algorithm, to yield an extremely secure, highly flexible, low overhead digital system design methodology. At the architecture-level, the root cause of architectural attacks has been analyzed and we propose efficient architectural support to monitor suspicious events. When such an event is detected, flexible software protection scheme will be invoked accordingly to prevent the potential information leakage. At the circuit-level, we will utilize Delay-Insensitive Ternary Logic (DITL) to design the circuit hardware. DITL maintains the inherent side-channel attack resistance of asynchronous logic, but only requires one wire for delay-insensitive encoding (instead of the normal two wires per bit), such that load capacitance imbalance between a bit's two wires is eliminated and area overhead is reduced. To demonstrate the effectiveness and efficiency of the proposed multi-level side-channel attack mitigation circuit design methodology, we will design, fabricate, and test a MIPS-compatible embedded microprocessor utilizing the developed techniques and automated design flow.